Multicore chip integration, i.e., placing and routing, is generally performed using either a hierarchical approach or a flat approach. In the hierarchical approach, multiple cores and other functional logics are combined into one supercluster. Instances of this supercluster are then placed at the chip level. The supercluster tends to be large in dimension, thereby limiting chip floorplan options. Also, because the hierarchy associated with each supercluster instance must be traversed to make a design change at the chip level, it can become difficult to implement design changes or search for design solutions as required to satisfy chip performance specifications.
In the flat approach, all cores and functional logics are placed and routed at the chip level, thereby avoiding hierarchical chip integration boundaries. However, in the flat approach, the chip is considered as a whole during the place and route process. Therefore, the chip floorplan can vary widely from one location on the chip to another. Consequently, in the traditional flat approach, the entire chip may need to be considered as a whole in performing overall routing, timing, and design verification activities, thereby increasing the time and expense required to converge the chip to a final design. In view of the foregoing, an improved multicore chip place and route methodology is sought.